Test MP+dmb.sy+fri-rfi-addr-ctrlisb

AArch64 MP+dmb.sy+fri-rfi-addr-ctrlisb
"DMB.SYdWW Rfe Fri Rfi DpAddrdR DpCtrlIsbdR Fre"
Cycle=Rfi DpAddrdR DpCtrlIsbdR Fre DMB.SYdWW Rfe Fri
Relax=
Safe=Rfi Rfe Fri Fre DMB.SYdWW DpAddrdR DpCtrlIsbdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMB.SYdWW Rfe Fri Rfi DpAddrdR DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X6=z; 1:X8=x;
}
 P0          | P1                  ;
 MOV W0,#1   | LDR W0,[X1]         ;
 STR W0,[X1] | MOV W2,#2           ;
 DMB SY      | STR W2,[X1]         ;
 MOV W2,#1   | LDR W3,[X1]         ;
 STR W2,[X3] | EOR W4,W3,W3        ;
             | LDR W5,[X6,W4,SXTW] ;
             | CBNZ W5,LC00        ;
             | LC00:               ;
             | ISB                 ;
             | LDR W7,[X8]         ;
Observed
    y=2; x=1; 1:X7=0; 1:X3=2; 1:X0=1;