Test 3.LB+poxxs

AArch64 3.LB+poxxs
"PodRWXX RfeXX PodRWXX RfeXX PodRWXX RfeXX"
Cycle=RfeXX PodRWXX RfeXX PodRWXX RfeXX PodRWXX
Relax=
Safe=PodRW RfeXX
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Rf
Orig=PodRWXX RfeXX PodRWXX RfeXX PodRWXX RfeXX
{ ok=1;
0:X0=x; 0:X3=y; 0:X7=ok;
1:X0=y; 1:X3=z; 1:X7=ok;
2:X0=z; 2:X3=x; 2:X7=ok;
}
 P0              | P1              | P2              ;
 LDXR W1,[X0]    | LDXR W1,[X0]    | LDXR W1,[X0]    ;
 STXR W2,W1,[X0] | STXR W2,W1,[X0] | STXR W2,W1,[X0] ;
 CBNZ W2,Fail0   | CBNZ W2,Fail1   | CBNZ W2,Fail2   ;
 MOV W4,#1       | MOV W4,#1       | MOV W4,#1       ;
 LDXR W5,[X3]    | LDXR W5,[X3]    | LDXR W5,[X3]    ;
 STXR W2,W4,[X3] | STXR W2,W4,[X3] | STXR W2,W4,[X3] ;
 CBNZ W2,Fail0   | CBNZ W2,Fail1   | CBNZ W2,Fail2   ;
 B Exit0         | B Exit1         | B Exit2         ;
 Fail0:          | Fail1:          | Fail2:          ;
 MOV W6,#0       | MOV W6,#0       | MOV W6,#0       ;
 STR W6,[X7]     | STR W6,[X7]     | STR W6,[X7]     ;
 Exit0:          | Exit1:          | Exit2:          ;
Observed
    z=1; y=1; x=1; ok=1; 2:X5=0; 2:X1=1; 1:X5=0; 1:X1=1; 0:X5=0; 0:X1=1;