Test MP+dmb.sy+pos-ctrl-addr-ctrl-addr

AArch64 MP+dmb.sy+pos-ctrl-addr-ctrl-addr
"DMB.SYdWW Rfe PosRR DpCtrldR DpAddrdR DpCtrldR DpAddrdR Fre"
Cycle=Rfe PosRR DpCtrldR DpAddrdR DpCtrldR DpAddrdR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR DpCtrldR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMB.SYdWW Rfe PosRR DpCtrldR DpAddrdR DpCtrldR DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X7=a; 1:X9=b; 1:X12=x;
}
 P0          | P1                     ;
 MOV W0,#1   | LDR W0,[X1]            ;
 STR W0,[X1] | LDR W2,[X1]            ;
 DMB SY      | CBNZ W2,LC00           ;
 MOV W2,#1   | LC00:                  ;
 STR W2,[X3] | LDR W3,[X4]            ;
             | EOR W5,W3,W3           ;
             | LDR W6,[X7,W5,SXTW]    ;
             | CBNZ W6,LC01           ;
             | LC01:                  ;
             | LDR W8,[X9]            ;
             | EOR W10,W8,W8          ;
             | LDR W11,[X12,W10,SXTW] ;
Observed
    y=1; x=1; 1:X2=0; 1:X11=1; 1:X0=1;