Test R+popl+dmb.sy

AArch64 R+popl+dmb.sy
"PodWWPL WseLP DMB.SYdWR Fre"
Cycle=Fre PodWWPL WseLP DMB.SYdWR
Relax=
Safe=Fre PodWW DMB.SYdWR WseLP
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=PodWWPL WseLP DMB.SYdWR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0           | P1          ;
 MOV W0,#1    | MOV W0,#2   ;
 STR W0,[X1]  | STR W0,[X1] ;
 MOV W2,#1    | DMB SY      ;
 STLR W2,[X3] | LDR W2,[X3] ;
exists
(y=2 /\ 1:X2=0)