Test MP+po+poxx+SYS2

AArch64 MP+po+poxx+SYS2
"PodWW RfePX PodRRXX FreXP"
Cycle=PodWW RfePX PodRRXX FreXP
Relax=RfePX FreXP
Safe=PodWW PodRR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWW RfePX PodRRXX FreXP
{
0:X1=x; 0:X3=y;
1:X0=y; 1:X3=x;
}
 P0          | P1              ;
 MOV W0,#1   | LDXR W1,[X0]    ;
 STR W0,[X1] | STXR W2,W1,[X0] ;
 MOV W2,#1   | LDXR W4,[X3]    ;
 STR W2,[X3] | STXR W5,W4,[X3] ;
exists
(x=1 /\ y=1 /\ 1:X5=0 /\ 1:X2=0 /\ 1:X1=1 /\ 1:X4=0)