Test MP+po+popx+SYS2

AArch64 MP+po+popx+SYS2
"PodWW Rfe PodRRPX FreXP"
Cycle=Rfe PodRRPX FreXP PodWW
Relax=FreXP
Safe=Rfe PodWW PodRR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWW Rfe PodRRPX FreXP
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X2=x;
}
 P0          | P1              ;
 MOV W0,#1   | LDR W0,[X1]     ;
 STR W0,[X1] | LDXR W3,[X2]    ;
 MOV W2,#1   | STXR W4,W3,[X2] ;
 STR W2,[X3] |                 ;
exists
(x=1 /\ 1:X4=0 /\ 1:X0=1 /\ 1:X3=0)