Test R+po+dmb.ld

AArch64 R+po+dmb.ld
"PodWW Wse DMB.LDdWR Fre"
Cycle=Fre PodWW Wse DMB.LDdWR
Relax=
Safe=Fre Wse PodWW DMB.LDdWR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=PodWW Wse DMB.LDdWR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 MOV W0,#1   | MOV W0,#2   ;
 STR W0,[X1] | STR W0,[X1] ;
 MOV W2,#1   | DMB LD      ;
 STR W2,[X3] | LDR W2,[X3] ;
exists
(y=2 /\ 1:X2=0)