Test R+dmb.sts

AArch64 R+dmb.sts
"DMB.STdWW Wse DMB.STdWR Fre"
Cycle=Fre DMB.STdWW Wse DMB.STdWR
Relax=
Safe=Fre Wse DMB.STdWW DMB.STdWR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=DMB.STdWW Wse DMB.STdWR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 MOV W0,#1   | MOV W0,#2   ;
 STR W0,[X1] | STR W0,[X1] ;
 DMB ST      | DMB ST      ;
 MOV W2,#1   | LDR W2,[X3] ;
 STR W2,[X3] |             ;
exists
(y=2 /\ 1:X2=0)