Test R+dmb.st+po

AArch64 R+dmb.st+po
"DMB.STdWW Wse PodWR Fre"
Cycle=Fre DMB.STdWW Wse PodWR
Relax=
Safe=Fre Wse PodWR DMB.STdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=DMB.STdWW Wse PodWR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 MOV W0,#1   | MOV W0,#2   ;
 STR W0,[X1] | STR W0,[X1] ;
 DMB ST      | LDR W2,[X3] ;
 MOV W2,#1   |             ;
 STR W2,[X3] |             ;
exists
(y=2 /\ 1:X2=0)