Test LB+dmb.sy+po

AArch64 LB+dmb.sy+po
"DMB.SYdRW Rfe PodRW Rfe"
Cycle=Rfe PodRW Rfe DMB.SYdRW
Relax=
Safe=Rfe PodRW DMB.SYdRW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DMB.SYdRW Rfe PodRW Rfe
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 LDR W0,[X1] | LDR W0,[X1] ;
 DMB SY      | MOV W2,#1   ;
 MOV W2,#1   | STR W2,[X3] ;
 STR W2,[X3] |             ;
exists
(0:X0=1 /\ 1:X0=1)