Test WRR+2W+poaa+dmb.sy+L

AArch64 WRR+2W+poaa+dmb.sy+L
"RfeLA PodRRAA FreAP DMB.SYdWW WsePL"
Cycle=DMB.SYdWW WsePL RfeLA PodRRAA FreAP
Relax=PodRRAA
Safe=Fre DMB.SYdWW [WsePL,RfeLP]
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=RfeLA PodRRAA FreAP DMB.SYdWW WsePL
{
0:X1=x;
1:X1=x; 1:X3=y;
2:X1=y; 2:X3=x;
}
 P0           | P1           | P2          ;
 MOV W0,#2    | LDAR W0,[X1] | MOV W0,#1   ;
 STLR W0,[X1] | LDAR W2,[X3] | STR W0,[X1] ;
              |              | DMB SY      ;
              |              | MOV W2,#1   ;
              |              | STR W2,[X3] ;
exists
(x=2 /\ 1:X0=2 /\ 1:X2=0)