Test Z6.4

AArch64 Z6.4
"PodWW Wse PodWR Fre PodWR Fre"
Cycle=Fre PodWW Wse PodWR Fre PodWR
Relax=
Safe=Fre Wse PodWW PodWR
Prefetch=0:x=F,0:y=W,1:y=F,1:z=T,2:z=F,2:x=T
Com=Ws Fr Fr
Orig=PodWW Wse PodWR Fre PodWR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z;
2:X1=z; 2:X3=x;
}
 P0          | P1          | P2          ;
 MOV W0,#1   | MOV W0,#2   | MOV W0,#1   ;
 STR W0,[X1] | STR W0,[X1] | STR W0,[X1] ;
 MOV W2,#1   | LDR W2,[X3] | LDR W2,[X3] ;
 STR W2,[X3] |             |             ;
exists
(y=2 /\ 1:X2=0 /\ 2:X2=0)