Test WRR+2W+pos+dmb.sys

AArch64 WRR+2W+pos+dmb.sys
"Rfe PosRR Fre DMB.SYsWW Wse"
Cycle=Rfe PosRR Fre DMB.SYsWW Wse
Relax=
Safe=Rfe Fre Wse PosRR DMB.SYsWW
Prefetch=
Com=Rf Fr Ws
Orig=Rfe PosRR Fre DMB.SYsWW Wse
{
0:X1=x;
1:X1=x;
2:X1=x;
}
 P0          | P1          | P2          ;
 MOV W0,#1   | LDR W0,[X1] | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1] | STR W0,[X1] ;
             |             | DMB SY      ;
             |             | MOV W2,#3   ;
             |             | STR W2,[X1] ;
Observed
    x=3; 1:X2=1; 1:X0=3;
and x=3; 1:X2=0; 1:X0=3;
and x=1; 1:X2=0; 1:X0=3;
and x=3; 1:X2=0; 1:X0=2;
and x=1; 1:X2=0; 1:X0=2;
and x=1; 1:X2=3; 1:X0=1;
and x=3; 1:X2=0; 1:X0=1;
and x=1; 1:X2=0; 1:X0=1;