Test Z6.2+dmb.sy+ctrl+dmb.st

AArch64 Z6.2+dmb.sy+ctrl+dmb.st
"DMB.SYdWW Rfe DpCtrldW Rfe DMB.STdRW Wse"
Cycle=Rfe DMB.STdRW Wse DMB.SYdWW Rfe DpCtrldW
Relax=
Safe=Rfe Wse DMB.STdRW DMB.SYdWW DpCtrldW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Ws
Orig=DMB.SYdWW Rfe DpCtrldW Rfe DMB.STdRW Wse
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z;
2:X1=z; 2:X3=x;
}
 P0          | P1           | P2          ;
 MOV W0,#2   | LDR W0,[X1]  | LDR W0,[X1] ;
 STR W0,[X1] | CBNZ W0,LC00 | DMB ST      ;
 DMB SY      | LC00:        | MOV W2,#1   ;
 MOV W2,#1   | MOV W2,#1    | STR W2,[X3] ;
 STR W2,[X3] | STR W2,[X3]  |             ;
Observed
    x=2; 2:X0=1; 1:X0=1;