Test Z6.2+dmb.st+dmb.st+data

AArch64 Z6.2+dmb.st+dmb.st+data
"DMB.STdWW Rfe DMB.STdRW Rfe DpDatadW Wse"
Cycle=Rfe DMB.STdRW Rfe DpDatadW Wse DMB.STdWW
Relax=
Safe=Rfe Wse DMB.STdWW DMB.STdRW DpDatadW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Ws
Orig=DMB.STdWW Rfe DMB.STdRW Rfe DpDatadW Wse
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z;
2:X1=z; 2:X3=x;
}
 P0          | P1          | P2           ;
 MOV W0,#2   | LDR W0,[X1] | LDR W0,[X1]  ;
 STR W0,[X1] | DMB ST      | EOR W2,W0,W0 ;
 DMB ST      | MOV W2,#1   | ADD W2,W2,#1 ;
 MOV W2,#1   | STR W2,[X3] | STR W2,[X3]  ;
 STR W2,[X3] |             |              ;
Observed
    x=2; 2:X0=1; 1:X0=1;