Test Z6.0+dmb.sy+dmb.st+dmb.sy

AArch64 Z6.0+dmb.sy+dmb.st+dmb.sy
"DMB.SYdWW Rfe DMB.STdRW Wse DMB.SYdWR Fre"
Cycle=Rfe DMB.STdRW Wse DMB.SYdWR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre Wse DMB.STdRW DMB.SYdWW DMB.SYdWR
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Ws Fr
Orig=DMB.SYdWW Rfe DMB.STdRW Wse DMB.SYdWR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z;
2:X1=z; 2:X3=x;
}
 P0          | P1          | P2          ;
 MOV W0,#1   | LDR W0,[X1] | MOV W0,#2   ;
 STR W0,[X1] | DMB ST      | STR W0,[X1] ;
 DMB SY      | MOV W2,#1   | DMB SY      ;
 MOV W2,#1   | STR W2,[X3] | LDR W2,[X3] ;
 STR W2,[X3] |             |             ;
Observed
    z=2; 2:X2=0; 1:X0=1;