Test WWC+dmb.ld+dmb.st

AArch64 WWC+dmb.ld+dmb.st
"Rfe DMB.LDdRW Rfe DMB.STdRW Wse"
Cycle=Rfe DMB.LDdRW Rfe DMB.STdRW Wse
Relax=
Safe=Rfe Wse DMB.LDdRW DMB.STdRW
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=Rfe DMB.LDdRW Rfe DMB.STdRW Wse
{
0:X1=x;
1:X1=x; 1:X3=y;
2:X1=y; 2:X3=x;
}
 P0          | P1          | P2          ;
 MOV W0,#2   | LDR W0,[X1] | LDR W0,[X1] ;
 STR W0,[X1] | DMB LD      | DMB ST      ;
             | MOV W2,#1   | MOV W2,#1   ;
             | STR W2,[X3] | STR W2,[X3] ;
Observed
    x=2; 2:X0=1; 1:X0=2;
and x=2; 2:X0=1; 1:X0=1;
and x=1; 2:X0=1; 1:X0=1;