Test LB+dmb.ld+dmb.st

AArch64 LB+dmb.ld+dmb.st
"DMB.LDdRW Rfe DMB.STdRW Rfe"
Cycle=Rfe DMB.LDdRW Rfe DMB.STdRW
Relax=
Safe=Rfe DMB.LDdRW DMB.STdRW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DMB.LDdRW Rfe DMB.STdRW Rfe
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 LDR W0,[X1] | LDR W0,[X1] ;
 DMB LD      | DMB ST      ;
 MOV W2,#1   | MOV W2,#1   ;
 STR W2,[X3] | STR W2,[X3] ;
Observed
    1:X0=1; 0:X0=1;