Test ISA2+dmb.sy+dmb.st+ctrlisb

AArch64 ISA2+dmb.sy+dmb.st+ctrlisb
"DMB.SYdWW Rfe DMB.STdRW Rfe DpCtrlIsbdR Fre"
Cycle=Rfe DMB.STdRW Rfe DpCtrlIsbdR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre DMB.STdRW DMB.SYdWW DpCtrlIsbdR
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Rf Fr
Orig=DMB.SYdWW Rfe DMB.STdRW Rfe DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z;
2:X1=z; 2:X3=x;
}
 P0          | P1          | P2           ;
 MOV W0,#1   | LDR W0,[X1] | LDR W0,[X1]  ;
 STR W0,[X1] | DMB ST      | CBNZ W0,LC00 ;
 DMB SY      | MOV W2,#1   | LC00:        ;
 MOV W2,#1   | STR W2,[X3] | ISB          ;
 STR W2,[X3] |             | LDR W2,[X3]  ;
Observed
    2:X2=0; 2:X0=1; 1:X0=1;