In this document we provide raw model and hardware logs:
We first briefly describe the columns of the table above:
-
Test
- Test sources.
- Model
- Raw model output, as generated by the
herd simulator.
Models are power.cat for Power and arm.cat for ARM.
Notice that those files can be reconstructed with herd.
For instance, one can reconstruct the Power model log by issuing the command
herd -model power.cat power-tests/@all.
- Operational
- Raw ppcmem output (no options).
- Hardware
- The sum of all the logs of all our experiments.
- Validation
- Those files provide a summary of experiments.
More precisely they give the validation status (Ok/No)
of each test, both for model and hardware logs.
The files are in a simple three column format:
name of test,
model validation, and hardware validation.
Notice that validation is performed w.r.t. the final condition of the test,
which is part of test source.
This document was translated from LATEX by
HEVEA.