Test ISA2+dmb+pos-po+addr

Executions for behaviour: "1:R0=0 ; 1:R1=0 ; 2:R0=0 ; 2:R2=0"

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R0=0 ; 2:R2=0"

Executions for behaviour: "1:R0=0 ; 1:R1=1 ; 2:R0=0 ; 2:R2=0"

Executions for behaviour: "1:R0=1 ; 1:R1=1 ; 2:R0=0 ; 2:R2=0"

Executions for behaviour: "1:R0=0 ; 1:R1=0 ; 2:R0=1 ; 2:R2=0"

Executions for behaviour: "1:R0=0 ; 1:R1=1 ; 2:R0=1 ; 2:R2=0"

Executions for behaviour: "1:R0=0 ; 1:R1=0 ; 2:R0=0 ; 2:R2=1"

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R0=0 ; 2:R2=1"

Executions for behaviour: "1:R0=0 ; 1:R1=1 ; 2:R0=0 ; 2:R2=1"

Executions for behaviour: "1:R0=1 ; 1:R1=1 ; 2:R0=0 ; 2:R2=1"

Executions for behaviour: "1:R0=0 ; 1:R1=0 ; 2:R0=1 ; 2:R2=1"

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R2=1"

Executions for behaviour: "1:R0=0 ; 1:R1=1 ; 2:R0=1 ; 2:R2=1"

Executions for behaviour: "1:R0=1 ; 1:R1=1 ; 2:R0=1 ; 2:R2=1"

ARM ISA2+dmb+pos-po+addr
"DMBdWW Rfe PosRR PodRW Rfe DpAddrdR Fre"
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Rf Fr
Orig=DMBdWW Rfe PosRR PodRW Rfe DpAddrdR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0           | P1           | P2              ;
 MOV R0,#1    | LDR R0,[%y1] | LDR R0,[%z2]    ;
 STR R0,[%x0] | LDR R1,[%y1] | EOR R1,R0,R0    ;
 DMB          | MOV R2,#1    | LDR R2,[R1,%x2] ;
 MOV R1,#1    | STR R2,[%z1] |                 ;
 STR R1,[%y0] |              |                 ;
exists (1:R0=0 /\ 1:R1=0 /\ 2:R0=0 /\ 2:R2=0) \/ (1:R0=0 /\ 1:R1=0 /\ 2:R0=0 /\ 2:R2=1) \/ (1:R0=0 /\ 1:R1=0 /\ 2:R0=1 /\ 2:R2=0) \/ (1:R0=0 /\ 1:R1=0 /\ 2:R0=1 /\ 2:R2=1) \/ (1:R0=0 /\ 1:R1=1 /\ 2:R0=0 /\ 2:R2=0) \/ (1:R0=0 /\ 1:R1=1 /\ 2:R0=0 /\ 2:R2=1) \/ (1:R0=0 /\ 1:R1=1 /\ 2:R0=1 /\ 2:R2=0) \/ (1:R0=0 /\ 1:R1=1 /\ 2:R0=1 /\ 2:R2=1) \/ (1:R0=1 /\ 1:R1=0 /\ 2:R0=0 /\ 2:R2=0) \/ (1:R0=1 /\ 1:R1=0 /\ 2:R0=0 /\ 2:R2=1) \/ (1:R0=1 /\ 1:R1=0 /\ 2:R0=1 /\ 2:R2=1) \/ (1:R0=1 /\ 1:R1=1 /\ 2:R0=0 /\ 2:R2=0) \/ (1:R0=1 /\ 1:R1=1 /\ 2:R0=0 /\ 2:R2=1) \/ (1:R0=1 /\ 1:R1=1 /\ 2:R0=1 /\ 2:R2=1)