Classification of the invalid executions of the ARM llh model

• Contents

In this note we classify the execution that are forbidden by the ARM llh model, yet observed on hardware, or invalid executions. We use the classification of invalid states of the original model defined here.

The following two tables give the number of invalid tests and executions by batch. For instance the S batch gathers 3828 tests (4942960 executions), of which 15 (144 executions) invalidate the ARM llh model. One may observe that the sum of batch size as number of executions (Row “Sum”) equals the number of all invalid executions (Row “All” in the right table below).

The All table gathers all invalid executions, with links to the relevant, more specific, batches on a test by test basis.

Invalid executions are observed only on quadcores implementations of the ARM architecture. We also give tables for those, namely Tegra3 and Exynos4412.

• Invalid behaviours in the ALL batch
• Invalid behaviours in the S batch
• Invalid behaviours in the T batch
• Invalid behaviours in the O batch
• Invalid behaviours in the P batch
• Invalid behaviours in the ST batch
• Invalid behaviours in the SO batch
• Invalid behaviours in the SP batch
• Invalid behaviours in the TO batch
• Invalid behaviours in the TP batch
• Invalid behaviours in the OP batch
• Invalid behaviours in the STO batch
• Invalid behaviours in the STP batch
• Invalid behaviours in the SOP batch
• Invalid behaviours in the TOP batch
• Invalid behaviours in the STOP batch
• Non classified executions
• Invalid executions by machine
  • Tegra3
  • Exynos4412

This document was translated from L^AT_EX by H^EV^EA.