Test LB+PPO0108

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; y=2"

ARM LB+PPO0108
"PodWW Rfe DpDatadW Rfe DpDatadW PosWW PosWR DpAddrdW"
Cycle=Rfe DpDatadW Rfe DpDatadW PosWW PosWR DpAddrdW PodWW
Relax=
Safe=Rfe PosWW PosWR Pod*W DpAddrdW DpDatadW
Prefetch=
Com=Rf Rf
Orig=PodWW Rfe DpDatadW Rfe DpDatadW PosWW PosWR DpAddrdW
{
%a0=a; %x0=x;
%x1=x; %y1=y; %z1=z; %a1=a;
}
 P0           | P1              ;
 LDR R0,[%a0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | EOR R1,R0,R0    ;
 ADD R1,R1,#1 | ADD R1,R1,#1    ;
 STR R1,[%x0] | STR R1,[%y1]    ;
              | MOV R2,#2       ;
              | STR R2,[%y1]    ;
              | LDR R3,[%y1]    ;
              | EOR R4,R3,R3    ;
              | MOV R5,#1       ;
              | STR R5,[R4,%z1] ;
              | MOV R6,#1       ;
              | STR R6,[%a1]    ;
Observed
    0:R0=1; 1:R0=1; y=2;