Test S+dmb+fri-rfi-addr-pos-fri

Executions for behaviour: "1:R0=0 ; 1:R2=2 ; 1:R4=2 ; 1:R5=0 ; x=1 ; y=1"

Executions for behaviour: "1:R0=0 ; 1:R2=2 ; 1:R4=2 ; 1:R5=0 ; x=1 ; y=2"

Executions for behaviour: "1:R0=1 ; 1:R2=2 ; 1:R4=2 ; 1:R5=0 ; x=1 ; y=2"

Executions for behaviour: "1:R0=1 ; 1:R2=2 ; 1:R4=0 ; 1:R5=0 ; x=2 ; y=2"

ARM S+dmb+fri-rfi-addr-pos-fri
"DMBdWW Rfe Fri Rfi DpAddrdR PosRR Fri Wse"
Cycle=Rfi DpAddrdR PosRR Fri Wse DMBdWW Rfe Fri
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMBdWW Rfe Fri Rfi DpAddrdR PosRR Fri Wse
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1              ;
 MOV R0,#2    | LDR R0,[%y1]    ;
 STR R0,[%x0] | MOV R1,#2       ;
 DMB          | STR R1,[%y1]    ;
 MOV R1,#1    | LDR R2,[%y1]    ;
 STR R1,[%y0] | EOR R3,R2,R2    ;
              | LDR R4,[R3,%x1] ;
              | LDR R5,[%x1]    ;
              | MOV R6,#1       ;
              | STR R6,[%x1]    ;
Observed
    1:R0=0; 1:R2=2; 1:R4=2; 1:R5=0; x=1; y=1;
and 1:R0=0; 1:R2=2; 1:R4=2; 1:R5=0; x=1; y=2;
and 1:R0=1; 1:R2=2; 1:R4=2; 1:R5=0; x=1; y=2;
and 1:R0=1; 1:R2=2; 1:R4=0; 1:R5=0; x=2; y=2;