Test Z6.0+dsb+ctrlisb+dsb.st

ARM Z6.0+dsb+ctrlisb+dsb.st
"DSBdWW Rfe DpCtrlIsbdW Wse DSB.STdWR Fre"
Cycle=Rfe DpCtrlIsbdW Wse DSB.STdWR Fre DSBdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Ws Fr
Orig=DSBdWW Rfe DpCtrlIsbdW Wse DSB.STdWR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0           | P1           | P2           ;
 MOV R0,#1    | LDR R0,[%y1] | MOV R0,#2    ;
 STR R0,[%x0] | CMP R0,R0    | STR R0,[%z2] ;
 DSB          | BNE LC00     | DSB ST       ;
 MOV R1,#1    | LC00:        | LDR R1,[%x2] ;
 STR R1,[%y0] | ISB          |              ;
              | MOV R1,#1    |              ;
              | STR R1,[%z1] |              ;
Observed
    1:R0=1; 2:R1=0; z=2;