Test WWC+dsb.st+addr

ARM WWC+dsb.st+addr
"Rfe DSB.STdRW Rfe DpAddrdW Wse"
Cycle=Rfe DSB.STdRW Rfe DpAddrdW Wse
Prefetch=0:x=F,1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=Rfe DSB.STdRW Rfe DpAddrdW Wse
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1           | P2              ;
 MOV R0,#2    | LDR R0,[%x1] | LDR R0,[%y2]    ;
 STR R0,[%x0] | DSB ST       | EOR R1,R0,R0    ;
              | MOV R1,#1    | MOV R2,#1       ;
              | STR R1,[%y1] | STR R2,[R1,%x2] ;
Observed
    1:R0=1; 2:R0=1; x=1;
and 1:R0=1; 2:R0=1; x=2;
and 1:R0=2; 2:R0=1; x=2;