Test WRC+data+dmb

ARM WRC+data+dmb
"Rfe DpDatadW Rfe DMBdRR Fre"
Cycle=Rfe DMBdRR Fre Rfe DpDatadW
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1             | P2            ;
 MOV R0, #1    | LDR R0, [%x1]  | LDR R0, [%y2] ;
 STR R0, [%x0] | EOR R1,R0,R0   | DMB           ;
               | ADD R1, R1, #1 | LDR R1, [%x2] ;
               | STR R1, [%y1]  |               ;
Observed
    1:R0=1; 2:R0=1; 2:R1=0;