Test WRC+ctrlisb+dsb.st

ARM WRC+ctrlisb+dsb.st
"Rfe DpCtrlIsbdW Rfe DSB.STdRR Fre"
Cycle=Rfe DSB.STdRR Fre Rfe DpCtrlIsbdW
Prefetch=0:x=T,1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=Rfe DpCtrlIsbdW Rfe DSB.STdRR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1           | P2           ;
 MOV R0,#1    | LDR R0,[%x1] | LDR R0,[%y2] ;
 STR R0,[%x0] | CMP R0,R0    | DSB ST       ;
              | BNE LC00     | LDR R1,[%x2] ;
              | LC00:        |              ;
              | ISB          |              ;
              | MOV R1,#1    |              ;
              | STR R1,[%y1] |              ;
Observed
    1:R0=1; 2:R0=1; 2:R1=0;