Test LB+data+detrw-wsi-rfi-addr

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ARM LB+data+detrw-wsi-rfi-addr
"DpDatadW Rfe DetourRW Wsi Rfi DpAddrdW Rfe"
Cycle=Rfi DpAddrdW Rfe DpDatadW Rfe DetourRW Wsi
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpDatadW Rfe DetourRW Wsi Rfi DpAddrdW Rfe
{
%x0=x; %y0=y;
%y1=y; %x1=x;
%y2=y;
}
 P0           | P1              | P2           ;
 LDR R0,[%x0] | LDR R0,[%y1]    | LDR R0,[%y2] ;
 EOR R1,R0,R0 | MOV R1,#3       | MOV R1,#2    ;
 ADD R1,R1,#1 | STR R1,[%y1]    | STR R1,[%y2] ;
 STR R1,[%y0] | MOV R2,#4       | DMB          ;
              | STR R2,[%y1]    | LDR R2,[%y2] ;
              | LDR R3,[%y1]    |              ;
              | EOR R4,R3,R3    |              ;
              | MOV R5,#1       |              ;
              | STR R5,[R4,%x1] |              ;
Observed
    0:R0=0; 1:R0=0; 1:R3=1; 2:R0=3; 2:R2=1; y=1;
and 0:R0=0; 1:R0=0; 1:R3=2; 2:R0=3; 2:R2=1; y=1;
and 0:R0=1; 1:R0=0; 1:R3=2; 2:R0=3; 2:R2=1; y=1;
and 0:R0=1; 1:R0=0; 1:R3=2; 2:R0=4; 2:R2=1; y=1;
and 0:R0=0; 1:R0=0; 1:R3=1; 2:R0=3; 2:R2=2; y=1;
and 0:R0=0; 1:R0=0; 1:R3=2; 2:R0=3; 2:R2=2; y=1;
and 0:R0=1; 1:R0=0; 1:R3=2; 2:R0=3; 2:R2=2; y=1;
and 0:R0=0; 1:R0=0; 1:R3=1; 2:R0=0; 2:R2=3; y=1;
and 0:R0=0; 1:R0=2; 1:R3=1; 2:R0=0; 2:R2=3; y=1;
and 0:R0=0; 1:R0=0; 1:R3=1; 2:R0=3; 2:R2=4; y=1;
and 0:R0=1; 1:R0=0; 1:R3=2; 2:R0=0; 2:R2=2; y=2;
and 0:R0=0; 1:R0=0; 1:R3=1; 2:R0=3; 2:R2=2; y=2;
and 0:R0=0; 1:R0=0; 1:R3=2; 2:R0=3; 2:R2=2; y=2;
and 0:R0=1; 1:R0=0; 1:R3=2; 2:R0=3; 2:R2=2; y=2;
and 0:R0=0; 1:R0=1; 1:R3=2; 2:R0=3; 2:R2=2; y=2;
and 0:R0=1; 1:R0=0; 1:R3=2; 2:R0=4; 2:R2=2; y=2;
and 0:R0=1; 1:R0=0; 1:R3=4; 2:R0=1; 2:R2=3; y=4;