Test 3.LB+dmb+ctrlisb+dmb.st

ARM 3.LB+dmb+ctrlisb+dmb.st
"DMBdRW Rfe DpCtrlIsbdW Rfe DMB.STdRW Rfe"
Cycle=Rfe DMBdRW Rfe DpCtrlIsbdW Rfe DMB.STdRW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Rf
Orig=DMBdRW Rfe DpCtrlIsbdW Rfe DMB.STdRW Rfe
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0           | P1           | P2           ;
 LDR R0,[%x0] | LDR R0,[%y1] | LDR R0,[%z2] ;
 DMB          | CMP R0,R0    | DMB ST       ;
 MOV R1,#1    | BNE LC00     | MOV R1,#1    ;
 STR R1,[%y0] | LC00:        | STR R1,[%x2] ;
              | ISB          |              ;
              | MOV R1,#1    |              ;
              | STR R1,[%z1] |              ;
Observed
    0:R0=1; 1:R0=1; 2:R0=1;