Test WRR+2W+ctrlisb+dmb.st

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; x=1"

ARM WRR+2W+ctrlisb+dmb.st
"Rfe DpCtrlIsbdR Fre DMB.STdWW Wse"
Cycle=Rfe DpCtrlIsbdR Fre DMB.STdWW Wse
Prefetch=0:x=F,1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=Rfe DpCtrlIsbdR Fre DMB.STdWW Wse
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1           | P2           ;
 MOV R0,#2    | LDR R0,[%x1] | MOV R0,#1    ;
 STR R0,[%x0] | CMP R0,R0    | STR R0,[%y2] ;
              | BNE LC00     | DMB ST       ;
              | LC00:        | MOV R1,#1    ;
              | ISB          | STR R1,[%x2] ;
              | LDR R1,[%y1] |              ;
Observed
    1:R0=1; 1:R1=0; x=1;