Test S+dmb+fri-rfi-pos-ctrl-rfi-ctrl

Executions for behaviour: "1:R0=0 ; 1:R2=1 ; 1:R3=2 ; 1:R5=1 ; x=1 ; y=1"

Executions for behaviour: "1:R0=0 ; 1:R2=1 ; 1:R3=2 ; 1:R5=1 ; x=2 ; y=1"

Executions for behaviour: "1:R0=1 ; 1:R2=2 ; 1:R3=2 ; 1:R5=1 ; x=2 ; y=2"

ARM S+dmb+fri-rfi-pos-ctrl-rfi-ctrl
"DMBdWW Rfe Fri Rfi PosRR DpCtrldW Rfi DpCtrldW Wse"
Cycle=Rfi PosRR DpCtrldW Rfi DpCtrldW Wse DMBdWW Rfe Fri
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMBdWW Rfe Fri Rfi PosRR DpCtrldW Rfi DpCtrldW Wse
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0           | P1           ;
 MOV R0,#2    | LDR R0,[%y1] ;
 STR R0,[%x0] | MOV R1,#2    ;
 DMB          | STR R1,[%y1] ;
 MOV R1,#1    | LDR R2,[%y1] ;
 STR R1,[%y0] | LDR R3,[%y1] ;
              | CMP R3,R3    ;
              | BNE LC00     ;
              | LC00:        ;
              | MOV R4,#1    ;
              | STR R4,[%z1] ;
              | LDR R5,[%z1] ;
              | CMP R5,R5    ;
              | BNE LC01     ;
              | LC01:        ;
              | MOV R6,#1    ;
              | STR R6,[%x1] ;
Observed
    1:R0=0; 1:R2=1; 1:R3=2; 1:R5=1; x=1; y=1;
and 1:R0=0; 1:R2=1; 1:R3=2; 1:R5=1; x=2; y=1;
and 1:R0=1; 1:R2=2; 1:R3=2; 1:R5=1; x=2; y=2;