Test S+PPO762

Executions for behaviour: "1:R0=1 ; x=2"

…

ARM S+PPO762
"Wse DMBdWW Rfe PosRR DpAddrdR PosRW PosWR DpCtrldW"
Cycle=Rfe PosRR DpAddrdR PosRW PosWR DpCtrldW Wse DMBdWW
Relax=
Safe=Rfe Wse PosWR PosRW PosRR DMBdWW DpAddrdR DpCtrldW
Prefetch=0:x=F,1:x=W
Orig=Wse DMBdWW Rfe PosRR DpAddrdR PosRW PosWR DpCtrldW
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0            | P1               ;
 MOV R0, #2    | LDR R0, [%y1]    ;
 STR R0, [%x0] | LDR R1, [%y1]    ;
 DMB           | EOR R2,R1,R1     ;
 MOV R1, #1    | LDR R3, [R2,%z1] ;
 STR R1, [%y0] | MOV R4, #1       ;
               | STR R4, [%z1]    ;
               | LDR R5, [%z1]    ;
               | CMP R5, R5       ;
               | BNE LC00         ;
               | LC00:            ;
               | MOV R6, #1       ;
               | STR R6, [%x1]    ;
Observed
    1:R0=1; x=2;