Test S+PPO537

Executions for behaviour: "1:R0=1 ; x=2"

…

ARM S+PPO537
"Wse DMBdWW Rfe PosRR DpDatadW PosWR PosRR DpDatadW"
Cycle=Rfe PosRR DpDatadW PosWR PosRR DpDatadW Wse DMBdWW
Relax=
Safe=Rfe Wse PosWR PosRR DMBdWW DpDatadW
Prefetch=0:x=F,1:x=W
Orig=Wse DMBdWW Rfe PosRR DpDatadW PosWR PosRR DpDatadW
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0            | P1             ;
 MOV R0, #2    | LDR R0, [%y1]  ;
 STR R0, [%x0] | LDR R1, [%y1]  ;
 DMB           | EOR R2,R1,R1   ;
 MOV R1, #1    | ADD R2, R2, #1 ;
 STR R1, [%y0] | STR R2, [%z1]  ;
               | LDR R3, [%z1]  ;
               | LDR R4, [%z1]  ;
               | EOR R5,R4,R4   ;
               | ADD R5, R5, #1 ;
               | STR R5, [%x1]  ;
Observed
    1:R0=1; x=2;