Test MP+dmb+pos-addr

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 1:R3=0"

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 1:R3=1"

ARM MP+dmb+pos-addr
"DMBdWW Rfe PosRR DpAddrdR Fre"
Cycle=Rfe PosRR DpAddrdR Fre DMBdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe PosRR DpAddrdR Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1              ;
 MOV R0,#1    | LDR R0,[%y1]    ;
 STR R0,[%x0] | LDR R1,[%y1]    ;
 DMB          | EOR R2,R1,R1    ;
 MOV R1,#1    | LDR R3,[R2,%x1] ;
 STR R1,[%y0] |                 ;
Observed
    1:R0=1; 1:R1=0; 1:R3=0;
and 1:R0=1; 1:R1=0; 1:R3=1;