Test MP+dmb+ctrl-detr

Executions for behaviour: "1:R0=0 ; 1:R1=1 ; 1:R2=0 ; x=1"

Executions for behaviour: "1:R0=1 ; 1:R1=1 ; 1:R2=0 ; x=1"

Executions for behaviour: "1:R0=0 ; 1:R1=2 ; 1:R2=0 ; x=1"

Executions for behaviour: "1:R0=1 ; 1:R1=2 ; 1:R2=0 ; x=1"

Executions for behaviour: "1:R0=0 ; 1:R1=1 ; 1:R2=2 ; x=1"

Executions for behaviour: "1:R0=1 ; 1:R1=1 ; 1:R2=2 ; x=1"

Executions for behaviour: "1:R0=0 ; 1:R1=1 ; 1:R2=0 ; x=2"

Executions for behaviour: "1:R0=0 ; 1:R1=2 ; 1:R2=0 ; x=2"

Executions for behaviour: "1:R0=1 ; 1:R1=2 ; 1:R2=0 ; x=2"

Executions for behaviour: "1:R0=0 ; 1:R1=2 ; 1:R2=1 ; x=2"

Executions for behaviour: "1:R0=1 ; 1:R1=2 ; 1:R2=1 ; x=2"

ARM MP+dmb+ctrl-detr
"DMBdWW Rfe DpCtrldR DetourR Fre"
Cycle=Rfe DpCtrldR DetourR Fre DMBdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe DpCtrldR DetourR Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
%x2=x;
}
 P0           | P1           | P2           ;
 MOV R0,#2    | LDR R0,[%y1] | MOV R0,#1    ;
 STR R0,[%x0] | CMP R0,R0    | STR R0,[%x2] ;
 DMB          | BNE LC00     |              ;
 MOV R1,#1    | LC00:        |              ;
 STR R1,[%y0] | LDR R1,[%x1] |              ;
              | LDR R2,[%x1] |              ;
Observed
    1:R0=0; 1:R1=1; 1:R2=0; x=1;
and 1:R0=1; 1:R1=1; 1:R2=0; x=1;
and 1:R0=0; 1:R1=2; 1:R2=0; x=1;
and 1:R0=1; 1:R1=2; 1:R2=0; x=1;
and 1:R0=0; 1:R1=1; 1:R2=2; x=1;
and 1:R0=1; 1:R1=1; 1:R2=2; x=1;
and 1:R0=0; 1:R1=1; 1:R2=0; x=2;
and 1:R0=0; 1:R1=2; 1:R2=0; x=2;
and 1:R0=1; 1:R1=2; 1:R2=0; x=2;
and 1:R0=0; 1:R1=2; 1:R2=1; x=2;
and 1:R0=1; 1:R1=2; 1:R2=1; x=2;