Test MP+dmb+ctrl-addr-detr

Executions for behaviour: "1:R0=0 ; 1:R3=1 ; 1:R4=0 ; x=1"

Executions for behaviour: "1:R0=1 ; 1:R3=1 ; 1:R4=0 ; x=1"

Executions for behaviour: "1:R0=0 ; 1:R3=2 ; 1:R4=0 ; x=1"

Executions for behaviour: "1:R0=1 ; 1:R3=2 ; 1:R4=0 ; x=1"

Executions for behaviour: "1:R0=0 ; 1:R3=1 ; 1:R4=2 ; x=1"

Executions for behaviour: "1:R0=1 ; 1:R3=1 ; 1:R4=2 ; x=1"

Executions for behaviour: "1:R0=0 ; 1:R3=1 ; 1:R4=0 ; x=2"

Executions for behaviour: "1:R0=0 ; 1:R3=2 ; 1:R4=0 ; x=2"

Executions for behaviour: "1:R0=1 ; 1:R3=2 ; 1:R4=0 ; x=2"

Executions for behaviour: "1:R0=0 ; 1:R3=2 ; 1:R4=1 ; x=2"

Executions for behaviour: "1:R0=1 ; 1:R3=2 ; 1:R4=1 ; x=2"

ARM MP+dmb+ctrl-addr-detr
"DMBdWW Rfe DpCtrldR DpAddrdR DetourR Fre"
Cycle=Rfe DpCtrldR DpAddrdR DetourR Fre DMBdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe DpCtrldR DpAddrdR DetourR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
%x2=x;
}
 P0           | P1              | P2           ;
 MOV R0,#2    | LDR R0,[%y1]    | MOV R0,#1    ;
 STR R0,[%x0] | CMP R0,R0       | STR R0,[%x2] ;
 DMB          | BNE LC00        |              ;
 MOV R1,#1    | LC00:           |              ;
 STR R1,[%y0] | LDR R1,[%z1]    |              ;
              | EOR R2,R1,R1    |              ;
              | LDR R3,[R2,%x1] |              ;
              | LDR R4,[%x1]    |              ;
Observed
    1:R0=0; 1:R3=1; 1:R4=0; x=1;
and 1:R0=1; 1:R3=1; 1:R4=0; x=1;
and 1:R0=0; 1:R3=2; 1:R4=0; x=1;
and 1:R0=1; 1:R3=2; 1:R4=0; x=1;
and 1:R0=0; 1:R3=1; 1:R4=2; x=1;
and 1:R0=1; 1:R3=1; 1:R4=2; x=1;
and 1:R0=0; 1:R3=1; 1:R4=0; x=2;
and 1:R0=0; 1:R3=2; 1:R4=0; x=2;
and 1:R0=1; 1:R3=2; 1:R4=0; x=2;
and 1:R0=0; 1:R3=2; 1:R4=1; x=2;
and 1:R0=1; 1:R3=2; 1:R4=1; x=2;