Test MP+PPO922

Executions for behaviour: "1:R0=1 ; 1:R5=1 ; x=2 ; y=2"

…

ARM MP+PPO922
"Fre DMBdWW Rfe PosRW PosWR DpDatadW PosWR PosRR"
Cycle=Rfe PosRW PosWR DpDatadW PosWR PosRR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWR PosRW PosRR DMBdWW DpDatadW
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe PosRW PosWR DpDatadW PosWR PosRR
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1             ;
 MOV R0, #2    | LDR R0, [%y1]  ;
 STR R0, [%x0] | MOV R1, #2     ;
 DMB           | STR R1, [%y1]  ;
 MOV R1, #1    | LDR R2, [%y1]  ;
 STR R1, [%y0] | EOR R3,R2,R2   ;
               | ADD R3, R3, #1 ;
               | STR R3, [%x1]  ;
               | LDR R4, [%x1]  ;
               | LDR R5, [%x1]  ;
Observed
    1:R0=1; 1:R5=1; x=2; y=2;