Test MP+PPO504

Executions for behaviour: "1:R0=1 ; 1:R8=1 ; x=2"

ARM MP+PPO504
"Fre DMBdWW Rfe PosRR DpDatadW PosWR DpAddrdR DpAddrdW PosWR"
Cycle=Rfe PosRR DpDatadW PosWR DpAddrdR DpAddrdW PosWR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWR PosRR DMBdWW DpAddrdW DpAddrdR DpDatadW
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe PosRR DpDatadW PosWR DpAddrdR DpAddrdW PosWR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0            | P1               ;
 MOV R0, #2    | LDR R0, [%y1]    ;
 STR R0, [%x0] | LDR R1, [%y1]    ;
 DMB           | EOR R2,R1,R1     ;
 MOV R1, #1    | ADD R2, R2, #1   ;
 STR R1, [%y0] | STR R2, [%z1]    ;
               | LDR R3, [%z1]    ;
               | EOR R4,R3,R3     ;
               | LDR R5, [R4,%a1] ;
               | EOR R6,R5,R5     ;
               | MOV R7, #1       ;
               | STR R7, [R6,%x1] ;
               | LDR R8, [%x1]    ;
Observed
    1:R0=1; 1:R8=1; x=2;