Test MP+PPO428

Executions for behaviour: "1:R0=1 ; 1:R2=0"

ARM MP+PPO428
"Fre DMBdWW Rfe PosRR DpCtrlIsbdR"
Cycle=Rfe PosRR DpCtrlIsbdR Fre DMBdWW
Relax=
Safe=Rfe Fre PosRR DMBdWW DpCtrlIsbdR
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe PosRR DpCtrlIsbdR
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 MOV R0, #1    | LDR R0, [%y1] ;
 STR R0, [%x0] | LDR R1, [%y1] ;
 DMB           | CMP R1, R1    ;
 MOV R1, #1    | BNE LC00      ;
 STR R1, [%y0] | LC00:         ;
               | ISB           ;
               | LDR R2, [%x1] ;
Observed
    1:R0=1; 1:R2=0;