Test MP+PPO041

Executions for behaviour: "1:R0=1 ; 1:R8=0"

…

ARM MP+PPO041
"Fre DMBdWW Rfe PosRR DpAddrdW PosWR DpDatadW PosWR DpAddrdR"
Cycle=Rfe PosRR DpAddrdW PosWR DpDatadW PosWR DpAddrdR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWR PosRR DMBdWW DpAddrdW DpAddrdR DpDatadW
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe PosRR DpAddrdW PosWR DpDatadW PosWR DpAddrdR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0            | P1               ;
 MOV R0, #1    | LDR R0, [%y1]    ;
 STR R0, [%x0] | LDR R1, [%y1]    ;
 DMB           | EOR R2,R1,R1     ;
 MOV R1, #1    | MOV R3, #1       ;
 STR R1, [%y0] | STR R3, [R2,%z1] ;
               | LDR R4, [%z1]    ;
               | EOR R5,R4,R4     ;
               | ADD R5, R5, #1   ;
               | STR R5, [%a1]    ;
               | LDR R6, [%a1]    ;
               | EOR R7,R6,R6     ;
               | LDR R8, [R7,%x1] ;
Observed
    1:R0=1; 1:R8=0;