Test LB+PPO0567

Executions for behaviour: "0:R0=1 ; 1:R0=1"

…

ARM LB+PPO0567
"PodRW Rfe DpDatadW Rfe PosRR DpAddrdR DpDatadW PosWR PosRR"
Cycle=Rfe PosRR DpAddrdR DpDatadW PosWR PosRR PodRW Rfe DpDatadW
Relax=
Safe=Rfe PosWR PosRR Pod*W DpAddrdR DpDatadW
Prefetch=
Com=Rf Rf
Orig=PodRW Rfe DpDatadW Rfe PosRR DpAddrdR DpDatadW PosWR PosRR
{
%a0=a; %x0=x;
%x1=x; %y1=y; %z1=z; %a1=a;
}
 P0           | P1              ;
 LDR R0,[%a0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | LDR R1,[%x1]    ;
 ADD R1,R1,#1 | EOR R2,R1,R1    ;
 STR R1,[%x0] | LDR R3,[R2,%y1] ;
              | EOR R4,R3,R3    ;
              | ADD R4,R4,#1    ;
              | STR R4,[%z1]    ;
              | LDR R5,[%z1]    ;
              | LDR R6,[%z1]    ;
              | MOV R7,#1       ;
              | STR R7,[%a1]    ;
Observed
    0:R0=1; 1:R0=1;