Test LB+PPO0523

Executions for behaviour: "0:R0=1 ; 1:R0=1"

…

ARM LB+PPO0523
"PodWW Rfe DpDatadW Rfe PosRR DpAddrdR PosRR PosRW"
Cycle=Rfe PosRR DpAddrdR PosRR PosRW PodWW Rfe DpDatadW
Relax=
Safe=Rfe PosRW PosRR Pod*W DpAddrdR DpDatadW
Prefetch=
Com=Rf Rf
Orig=PodWW Rfe DpDatadW Rfe PosRR DpAddrdR PosRR PosRW
{
%z0=z; %x0=x;
%x1=x; %y1=y; %z1=z;
}
 P0           | P1              ;
 LDR R0,[%z0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | LDR R1,[%x1]    ;
 ADD R1,R1,#1 | EOR R2,R1,R1    ;
 STR R1,[%x0] | LDR R3,[R2,%y1] ;
              | LDR R4,[%y1]    ;
              | MOV R5,#1       ;
              | STR R5,[%y1]    ;
              | MOV R6,#1       ;
              | STR R6,[%z1]    ;
Observed
    0:R0=1; 1:R0=1;