Executions for behaviour:
"0:R0=1 ; 1:R0=1"
ARM LB+PPO0118 "PodWW Rfe DpDatadW Rfe PosRR DpAddrdW" Cycle=Rfe PosRR DpAddrdW PodWW Rfe DpDatadW Relax= Safe=Rfe PosRR Pod*W DpAddrdW DpDatadW Prefetch= Com=Rf Rf Orig=PodWW Rfe DpDatadW Rfe PosRR DpAddrdW { %z0=z; %x0=x; %x1=x; %y1=y; %z1=z; } P0 | P1 ; LDR R0,[%z0] | LDR R0,[%x1] ; EOR R1,R0,R0 | LDR R1,[%x1] ; ADD R1,R1,#1 | EOR R2,R1,R1 ; STR R1,[%x0] | MOV R3,#1 ; | STR R3,[R2,%y1] ; | MOV R4,#1 ; | STR R4,[%z1] ; Observed 0:R0=1; 1:R0=1;