Test LB0068

Executions for behaviour: "0:R0=2 ; 1:R0=1 ; x=2"

ARM LB0068
"DpDatadW Rfe DpCtrldW PosWW Rfe"
Cycle=Rfe DpDatadW Rfe DpCtrldW PosWW
Relax=[Rfe,DpDatadW,Rfe]
Safe=PosWW DpCtrldW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpDatadW Rfe DpCtrldW PosWW Rfe
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 LDR R0,[%x0] | LDR R0,[%y1] ;
 EOR R1,R0,R0 | CMP R0,R0    ;
 ADD R1,R1,#1 | BNE LC00     ;
 STR R1,[%y0] | LC00:        ;
              | MOV R1,#1    ;
              | STR R1,[%x1] ;
              | MOV R2,#2    ;
              | STR R2,[%x1] ;
Observed
    0:R0=2; 1:R0=1; x=2;