Test LB+PPO0408

Executions for behaviour: "0:R0=1 ; 1:R0=1"

ARM LB+PPO0408
"PodRW Rfe DpDatadW Rfe DpAddrdR DpDatadW PosWR"
Cycle=Rfe DpAddrdR DpDatadW PosWR PodRW Rfe DpDatadW
Relax=
Safe=Rfe PosWR Pod*W DpAddrdR DpDatadW
Prefetch=
Com=Rf Rf
Orig=PodRW Rfe DpDatadW Rfe DpAddrdR DpDatadW PosWR
{
%a0=a; %x0=x;
%x1=x; %y1=y; %z1=z; %a1=a;
}
 P0           | P1              ;
 LDR R0,[%a0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | EOR R1,R0,R0    ;
 ADD R1,R1,#1 | LDR R2,[R1,%y1] ;
 STR R1,[%x0] | EOR R3,R2,R2    ;
              | ADD R3,R3,#1    ;
              | STR R3,[%z1]    ;
              | LDR R4,[%z1]    ;
              | MOV R5,#1       ;
              | STR R5,[%a1]    ;
Observed
    0:R0=1; 1:R0=1;