Test LB+PPO0022

Executions for behaviour: "0:R0=1 ; 1:R0=1"

ARM LB+PPO0022
"PodRW Rfe DpDatadW Rfe DpCtrldW PosWR DpCtrldW PosWR DpAddrdR"
Cycle=Rfe DpDatadW Rfe DpCtrldW PosWR DpCtrldW PosWR DpAddrdR PodRW
Relax=
Safe=Rfe PosWR Pod*W DpAddrdR DpDatadW DpCtrldW
Prefetch=
Com=Rf Rf
Orig=PodRW Rfe DpDatadW Rfe DpCtrldW PosWR DpCtrldW PosWR DpAddrdR
{
%b0=b; %x0=x;
%x1=x; %y1=y; %z1=z; %a1=a; %b1=b;
}
 P0           | P1              ;
 LDR R0,[%b0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | CMP R0,R0       ;
 ADD R1,R1,#1 | BNE LC00        ;
 STR R1,[%x0] | LC00:           ;
              | MOV R1,#1       ;
              | STR R1,[%y1]    ;
              | LDR R2,[%y1]    ;
              | CMP R2,R2       ;
              | BNE LC01        ;
              | LC01:           ;
              | MOV R3,#1       ;
              | STR R3,[%z1]    ;
              | LDR R4,[%z1]    ;
              | EOR R5,R4,R4    ;
              | LDR R6,[R5,%a1] ;
              | MOV R7,#1       ;
              | STR R7,[%b1]    ;
Observed
    0:R0=1; 1:R0=1;