Test S+PPO732

ARM S+PPO732
"Wse DMBdWW Rfe PosRW PosWR DpAddrdW PosWW PosWR DpCtrldW"
Cycle=Rfe PosRW PosWR DpAddrdW PosWW PosWR DpCtrldW Wse DMBdWW
Relax=
Safe=Rfe Wse PosWW PosWR PosRW DMBdWW DpAddrdW DpCtrldW
Prefetch=0:x=F,1:x=W
Orig=Wse DMBdWW Rfe PosRW PosWR DpAddrdW PosWW PosWR DpCtrldW
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0            | P1               ;
 MOV R0, #2    | LDR R0, [%y1]    ;
 STR R0, [%x0] | MOV R1, #2       ;
 DMB           | STR R1, [%y1]    ;
 MOV R1, #1    | LDR R2, [%y1]    ;
 STR R1, [%y0] | EOR R3,R2,R2     ;
               | MOV R4, #1       ;
               | STR R4, [R3,%z1] ;
               | MOV R5, #2       ;
               | STR R5, [%z1]    ;
               | LDR R6, [%z1]    ;
               | CMP R6, R6       ;
               | BNE LC00         ;
               | LC00:            ;
               | MOV R7, #1       ;
               | STR R7, [%x1]    ;
Observed
    1:R0=1; x=2; y=2; z=2;