Test MP+PPO482

ARM MP+PPO482
"Fre DMBdWW Rfe DpDatadW PosWW PosWR PosRR DpCtrlIsbdR"
Cycle=Rfe DpDatadW PosWW PosWR PosRR DpCtrlIsbdR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWW PosWR PosRR DMBdWW DpDatadW DpCtrlIsbdR
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe DpDatadW PosWW PosWR PosRR DpCtrlIsbdR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0            | P1             ;
 MOV R0, #1    | LDR R0, [%y1]  ;
 STR R0, [%x0] | EOR R1,R0,R0   ;
 DMB           | ADD R1, R1, #1 ;
 MOV R1, #1    | STR R1, [%z1]  ;
 STR R1, [%y0] | MOV R2, #2     ;
               | STR R2, [%z1]  ;
               | LDR R3, [%z1]  ;
               | LDR R4, [%z1]  ;
               | CMP R4, R4     ;
               | BNE LC00       ;
               | LC00:          ;
               | ISB            ;
               | LDR R5, [%x1]  ;
Observed
    1:R0=1; 1:R5=0; z=2;