Test MP+PPO246

ARM MP+PPO246
"Fre DMBdWW Rfe DpDatadW PosWW PosWR DpAddrdR DpCtrlIsbdR"
Cycle=Rfe DpDatadW PosWW PosWR DpAddrdR DpCtrlIsbdR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWW PosWR DMBdWW DpAddrdR DpDatadW DpCtrlIsbdR
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe DpDatadW PosWW PosWR DpAddrdR DpCtrlIsbdR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0            | P1               ;
 MOV R0, #1    | LDR R0, [%y1]    ;
 STR R0, [%x0] | EOR R1,R0,R0     ;
 DMB           | ADD R1, R1, #1   ;
 MOV R1, #1    | STR R1, [%z1]    ;
 STR R1, [%y0] | MOV R2, #2       ;
               | STR R2, [%z1]    ;
               | LDR R3, [%z1]    ;
               | EOR R4,R3,R3     ;
               | LDR R5, [R4,%a1] ;
               | CMP R5, R5       ;
               | BNE LC00         ;
               | LC00:            ;
               | ISB              ;
               | LDR R6, [%x1]    ;
Observed
    1:R0=1; 1:R6=0; z=2;